Increasing networking speeds and port densities have fueled the demand for memory arrays, such as dynamic random access memories (DRAMs), having high bandwidth memory. Although it may be possible to increase data transfer speeds by using a faster clock, DRAMs tend to be latency-intensive; that is, they often exhibit significant propagation delays between receipt of a data request and a data output responsive to the request. The delays are often large enough to overwhelm the clock, requiring a re-synchronization mechanism to synchronize the data output with, for example, a clock in a data receiving device, such as an application-specific integrated circuit (ASIC). Further, currently known memory arrays tend to have low bus efficiencies and/or low bandwidths due to limitations in the DRAM bus, such as restrictions in the direction and/or the amount of data that can be sent to and from arrays in the DRAM.
There is a desire for a system and method that combines faster speeds with high bandwidth and high bus efficiency.